Embodiments of the present invention relate generally to phase and delay locked loops, and more particularly, to a phase locked loop (PLL) or a delay locked loop (DLL) with chopper stabilized phase offset.
One common application for phase-locked loops (PLL) and delay-locked loops (DLL) is the regeneration of a clock signal for local use. In many cases, it is desirable that the regenerated clock signal be phase aligned to the reference clock signal. In principle, the PLL is very well suited to this task. A charge-pump PLL is used herein for this explanation, but it can be shown that the same principle applies to DLLs also. A charge-pump PLL or DLL device used in this way is often referred to as a “zero-delay buffer” (ZDB).
Referring to FIG. 1, an idealized conventional ZDB control circuit 100 using PLL can be viewed as a negative-feedback system. The ZDB control circuit 100 includes a phase frequency detector 102 that receives a clock signal, of reference phase ΦREF, as an input and a clock signal, with feedback phase ΦFBK, as control feedback. The phase frequency detector 102 provides “Up” and “Down” pulse signals to a charge-pump 104. When the reference phase leads (i.e., is earlier in time than) the feedback phase, “Up” pulses are generated that cause the charge-pump to add a quantity of charge to a loop filter 106. The quantity of charge is proportional to the phase difference and will increase the voltage on the loop filter 106 which is coupled to the charge-pump 104 and that, in turn, increases the frequency of a voltage controlled oscillator (VCO) 108. The frequency of the VCO 108 is, in fact, the rate of phase accumulation. So, the phase, ΦFBK, of the feedback clock edges will become advanced in time and closer to the phase of the reference edges. This process will continue until the phases are matched or aligned. Conversely, if the reference phase lags (i.e., is later in time than) the feedback phase, “Down” pulses are generated that will remove charge from the loop filter and the VCO frequency will go down. The phase of the feedback clock edges become delayed in time and closer to the phase of the reference edges. Again, this process will continue until the phases are aligned. The negative feedback seeks to always adjust the output frequency until both inputs to the phase-frequency detector 102 are identical, or aligned, in phase and frequency. Since the output of the VCO is directly connected to the ΦFBK input, the output now has the same phase and frequency as the ΦREF input, and thus, the origin of the term “zero-delay buffer.” It should be noted that a ZDB may also be used with a frequency divider inserted in the path between VCO output and ΦFBK input. In this case, the output frequency will be a multiple of the input frequency, but their phases will still be substantially aligned assuming that the divider delay is negligible.
A figure of merit of a ZDB is the average phase difference between the output and the input. This is commonly referred to as “static phase offset” (SPO). In many systems, if the SPO is not zero, or if it changes dynamically over time and temperature changes, the system timing margins will be directly degraded. There are many circuit effects which can cause the static phase offset of such a ZDB 100 to be non-zero, such as mismatch of charge-pump currents, “dead-zone” effect in the phase-frequency detector transfer function, asymmetrical charge transfer of Up and Down signals into the Loop filter, and Loop filter leakage current.
It is desirable to systematically reduce the SPO of a ZDB by a separate feedback loop. It is desirable for the separate feedback loop to be designed in such a way that errors, as described above, may be automatically detected and removed from the measurement. This is done without disturbance of the main loop of the PLL, which is a major advantage. It is desirable that the loop not be taken out of service to self-calibrate the phase detector and charge-pump, even for brief intervals. Interruptions in the normal sampling of phase error reduce the maximum allowable loop bandwidth that can be achieved with stability. It is desirable to provide a phase locked loop (PLL) or a delay locked loop (DLL) with chopper stabilized phase offset.